EDA Methodology: SKILL Routine to Define MOS Device Width
It is not very often that an organization is willing to give something away for free, but that is what Glew Engineering is doing right now.
Below is a sample written in SKILL language of a CDF callback procedure for generation of the width of a MOS device. Glew Engineering Consulting’s experts in EDA methodology can assist with your CAD EDA systems: Cadence(TM), Synopsys(TM), Mentor Graphics (TM) and more.
The SKILL procedure for use in EDA CAD for semiconductor engineering of integrated circuits (IC) and ASICS is fully functional and yours to try out. This is just a small sample of the many ways in which we can help with your EDA needs for semiconductor IC design. Contact Glew Engineering to discuss your CAD EDA, or any engineering work your business requires.