This article on process yields is our second in a series on semiconductor processing. This series is geared toward those who are not technical specialists in this field. In the semiconductor industry, yield is represented by the functionality and reliability of integrated circuits produced on the wafer surfaces.
[i] Some may argue that maintaining a high process yield is the most critical part of the semiconductor fabrication industry, as it is necessary to be able to produce chips at a profit. Much of the industry is solely focused on increasing process yields. This is due to the demanding nature of the process and the vast number of processes necessary to produce a packaged chip. Another important factor to consider is that most production mistakes on a semiconductor chip cannot be repaired. Below we will discuss the various process yields that are measured during the fabrication process, limiters to the wafer-fabrication yield, and steps that are commonly taken to help increase yield.
How Fab Yield is Calculated
The first major yield measurement is calculated at the completion of wafer fabrication and is known by various names that include fab yield, line yield, or accumulative fab yield. Fab yield is calculated by one of two ways. The first, and simplistic method is to dividing the number of wafers exiting the fabrication area by the number that began. A second, and more come way to calculate fab yield is to first calculate the station yield, for each individual process. Station yield is the number of wafers leaving a station divided by the number of wafers entering the station. Once the station yield is calculation for each process, they are multiplied together to determine the accumulated fab yield.
Wafer Fabrication Yield = Number of Wafers Out
Number of Wafers Started
Station Yield = Number of wafers leaving station
Number of wafers entering station
Accumulative Fab Yield = Y(station 1) x Y(station 2) x … Y(station n)
Common Limitations to Wafer-Fabrication Yield
Wafer-fabrication yield is limited by numerous factors. One of the primary factors is the vast number of processes necessary to fabricate a semiconductor chip. This multi step process requires each individual process to have a very high operation yield, in the 90% range, in order for the overall process to have an 85% accumulative fab yield. As the number of semiconductor processing steps increases, the likelihood that one of the other limiting factors will occur increases as well. Another limiter is wafer breakage and warping. Wafers are handled dozens of times during the fabrication process, with each time being an opportunity for the wafer to be damaged. The wafer must also remain completely flat, especially in fabrication lines that use patterning techniques that project the pattern onto the wafer. If the wafer is warped, the projected image will be distorted and nonfunctional. Another yield limiter is process variation. Each step in the fabrication process opens itself to variation from wafer-to-wafer, however automated processing helps to maintain control specifications within a normal distribution. Process defects are another yield limiter common in the fabrication process and are a small region of contamination or irregularity on the wafer surface. Sources of these defects include the various liquids, gases, personnel, and machines necessary to complete the fabrication process. One of the final limitations to process yield is a mask defect. A photomask or reticle is the source of the pattern that is transferred to the wafer. If the mask/reticle is defected, these defects will end up on the wafer. Common origins of these defects include contamination, cracks on the quartz, or pattern distortions that occur in the mask/reticle making process.
Wafer-Sort Yield Factors
Following fabrication, wafers move to the wafer sort tester, where each chip is tested electrically for specifications and functionality. This yield is calculated by dividing the number of functioning die by the number of die on a wafer.
Wafer Sort Yield = Number of Functioning Die
Number of Die on Wafer
These tests directly monitor the electrical performance of the devices while indirectly monitoring the cleanliness of the fabrication process. A wafer sort is a comprehensive test that is affected by many factors that could include wafer diameter, die size, and process cycle time.
Wafer Packaging Yield
After a wafer has passed through the wafer sort process, it moves on to the assembly, or semiconductor packaging, process. Here the chips are cut into die and packaged into a protective enclosure. During this process the chip goes through numerous visual inspections. Once the chip has been packaged it must then pass physical, environmental, and electrical tests. Once tests are completed the third major yield ration is calculated, as the number of packages passing final test divided by the number of die stared into packaging.
Packaging Yield = Number of Packaged Die Passing Final Test
# of Functioning Die Started into Packaging
Overall Process Yield
Once all three of the major yields are calculated, one can then calculate the overall process yield for the entire process. This is calculated by multiplying the three individual yields together, and is expressed as a percentage.
Wafer Fab Yield x Wafer Sort Yield x Packaging Yield = Overall Yield
Improving process yield is a main part of the semiconductor processing industry. Some common practices to improve yield include maintaining an extremely clean and sanitary work environment. This can be done through clean rooms and automation. Specific software is often used in semiconductor processing that can result in higher yields and lower defects. Yield optimization software cannot only provide analyses of the process, but also can make recommendations to the process that will result in yield improvements.
We hope that you found this review of process yields helpful. Please feel free to comment below and let the bloggers at Glew Engineering know if there is a specific topic you’d like us to blog about in the future.
Van Zant, P. (2000). Microchip fabrication, a practical guide to semiconductor processing. (4th ed.). New York, NY: McGraw-Hill.