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Tester-Prober Interfaces: Direct Probe and System Interface Implications

Image on the left courtesy of Advantest

In this installment of our blog series on Tester-Prober Interfaces and probers, we discuss the latest evolution of direct device under test (DUT) connection and the implications on the semiconductor wafer probing industry.  The move to Direct Probe™ benefits the end user with improvements in speed and testing performance, but causes difficulty for equipment designers implementing the new interface technique.  This article continues a series, part 1 reviewed the issue of interfacing a piece of Automatic Test Equipment (ATE) to the DUT, a wafer.  For more information on this topic click the link below:

https://www.glewengineering.com/blog/bid/105402/Tester-Prober-Interfaces-Direct-Probe-Part-1

Probe Cards and Impedance Matching

Figure 1: Generic Tester-Prober Interface Architecture

Figure 1 shows a generic model of a piece of  automatic test equipment, or “tester”. The ATE contains  the following main elements: (1) a workstation as the user interface and programming station, (2) a mainframe which houses all the power distribution and smarts to execute tests and collect returning data, and (3) a test head, usually at the end of a mechanical manipulator.  The test head of the ATE contains the actual instruments to drive signals, supply operating power, and measure response from the DUT (Roberts 12-13).

Analog instruments present impedance challenges, but for the purposes of high-speed memory and logic testing, the digital I/O is designed for 50 ohm transmission line impedance.  In order to maximize signal fidelity and minimize loss at speed, probe cards contain matching circuitry to terminate the test connections as close to the DUT as possible.  Even the signal paths through the probe card must be designed as transmission lines with internal impedances as close to 50 ohms as possible.

Modern probe cards and Device Interface Boards (DIB) cause additional complexity and cost. The probe cards and DIBs for the electrical engineers who design the printed circuit boards (PCB) to follow very complex design rules.  For example, the PCBs must have equal path lengths, and ground lines and ground planes to guard the signal lines.  This makes for higher layer count PCB, which increases cost.  Some high pin count PCBs now have 36 layers.

The impedance termination circuitry takes real estate on the boards and there just isn’t that much of it on a 9.5-inch or even a 12-inch round probe card.

Figure 2: Generic 12-inch Probe Card

Figure 2 shows a generic 12-inch diameter wafer probe card.  There is not much usable space for the circuitry on the PCB after excluding the contact areas for the POGO™ pins, the probe array, and stiffener.

High Pin Count Causes Excessive Probe Force

High pin count causes excessive probe force and deforms the PCB, thus degrading the probing precision.  High pin count probe cards also carry some serious mechanical burdens.  A typical tungsten probe tip (either vertical or cantilever) acts like a spring and exerts force based on its probing displacement.  Values vary but tend to hover in the range of 3gmf per 25um of compression.  A probe card for a Graphics Processing Unit (GPU) can have 4000 pins spread over a 1 square inch area.  If the probe card lands and compresses the pins by 75 micro- meter, then it causes a force of 36kg (79 psi).

As a result of the high pin count causing excessive probe force, mechanical engineers have reinforced stiffener frames, up to 1 inch thick, to keep the board flat.  In one case mechanical engineers employed a steel cap over the area of the probe array.  The PCB is thicker as a consequence of the high layer count and the need for additional stiffness.  Some probe cards are up to 0.25 inch thick, which increases cost.

Signal Fidelity Issues

Figure 3: I/O Connection Path

Figure 3 shows the POGO™ based connection path from test head to wafer.  Every point that a spring contact touches a PCB there is an insertion loss and slight mismatch between the ideal 50 ohm drive and the actual impedance of the board.  On top of that, the 4-5 inches of space separation through the POGO™ tower adds delay and attenuation to the signals.  These factors limit the upper-end performance of such probe card schemes to the tens of megahertz, depending on test conditions, voltage margins, etc.

There are still a lot of these POGO™ tower setups in fabs around the world.  I worked on diagnostic system designs and installations at some major players in New York and Dresden in 2013, and for their applications this scheme worked fine. This POGO™ tower isn’t dead by a long shot; it just has its limitations.

All-in-One Prober Interface

For those on the bleeding-edge of high-speed test in the GPU and CPU world, the Advantest V93000 Direct Probe™ test system has taken a major step towards improving signal integrity and test speed by combining the functions of the DUT board and probe card into a single high speed board.  At the same time, they have completely done away with the POGO™ tower.

Figure 4: Direct Probe vs. Conventional Interface.  Image courtesy of Advantest.

As Figure 4 shows, the Direct Probe scheme eliminates several signal transitions and cuts path length to the bare minimum.  An additional benefit is having more real estate in the central region of the essentially 480mm x 600mm probe card for signal conditioning, switching, and termination circuitry.

Figure 5: From 12-inch to 480mm x 600mm

Figure 5 shows a scale comparison between the 12-inch and the loadboard-sized probe card of the V93K.  The outer edges of the board are reserved for contact to the pin electronics but the middle third can get circuitry.

System Implications of Direct Probe

This technology boost comes at a price and the implications ripple outward to every supplier and maker of hardware that connects to Automatic Test Equipment.  I will go into some of these issues in more detail in later posts, but here are the high points (see figure 6):

Figure 6: V93000 Test Head.  Image courtesy of Advantest.

Probe Card

The surface area has quadrupled from about 113 to 446.4 square inches.  This turns an already expensive, high layer count PCB into a REALLY expensive PCB.  Such boards are easily in the 10s of thousands of dollars and I’ve seen some go over the 100K mark with a complex probe array attached.

The traditional stiffener design is not up to the probe force requirements.  It was designed with just the tester pin electronics in mind and is both too thin and has a large open area in the middle third where the probe array ends up.  Advantest’s solution to this problem was the creation of a huge bar of metal called the “Bridge Beam” that spans the central open area.  It also serves as a mounting location for wafer probers.

Wafer Prober

Because the board docks directly to the test head, this means that the test head of the ATE docks directly to the prober.  And, since the probe card wants to be mounted inside the prober, the implication is that the test head has to go into the prober.  This affects the whole mechanical architecture of the prober, from the top deck to internal probe card changer.  In my last company, I had to work out an entirely new system architecture for our tool.  We spent more than a year bringing it to market and had to solve major loading and vibration coupling issues.

Direct Probe™ technology has brought a major improvement to automatic test equipment, and is one of the factors that has kept Advantest on top for decades.  As a system design engineer who has designed automatic test equipment for decades, I duly appreciate this technology.

[/fusion_text][/fusion_builder_column][/fusion_builder_row][/fusion_builder_container][fusion_builder_container hundred_percent=”yes” overflow=”visible”][fusion_builder_row][fusion_builder_column type=”1_1″ layout=”1_1″ background_position=”left top” background_color=”” border_size=”” border_color=”” border_style=”solid” spacing=”yes” background_image=”” background_repeat=”no-repeat” padding=”” margin_top=”0px” margin_bottom=”0px” class=”” id=”” animation_type=”” animation_speed=”0.3″ animation_direction=”left” hide_on_mobile=”no” center_content=”no” min_height=”none” last=”no” hover_type=”none” link=”” border_position=”all”][fusion_text][1] Roberts, Gordon, and Mark Burns.  An Introduction to Mixed-Signal IC Test and Measurement.  New York: Oxford University Press, 2001.  Print.

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