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Series on Semiconductor Processing and Integrated Circuits, Part 6: Multilayer Photoresist Processing

Home/Materials Science, Mechanical Engineering, Semiconductor/Series on Semiconductor Processing and Integrated Circuits, Part 6: Multilayer Photoresist Processing

Series on Semiconductor Processing and Integrated Circuits, Part 6: Multilayer Photoresist Processing


Below is our sixth article in a series intended as an overview for those who are not technical specialists in this field.  We will briefly describe multilayer photoresist processing.

A basic ten step lithography process is based on a single photoresist layer, and assumes that the layer can resolve the necessary images without pinholes or failing during the etch process.  The sub-micron era has made variations to the single resist layer process necessary.


With numerous multilayer resist processes available, the choice depends on the size of the resist opening and the severity of the surface topography.  A multilayer resist process features a thicker bottom layer that fills in the valleys and planarizes the surface.  The image is first formed in a layer of photoresist on the top of the planarizing layer.  Surface imaging allows small dimension imaging because the surface is flat.  Two layers of photoresists, each with different polarity, are used in a dual multilayer resists process.  This process can resolve small geometries on wafers with a varied topography.  In the first step, a relatively thick layer of resist is applied and baked to the thermal flow point, with the goal of achieving a planar top resist surface.  The typical multilayer process will use a positive-acting polymethylmeth acrylate resist sensitive to deep ultraviolet radiation.  Secondly, a thin layer of positive resist sensitive to just ultraviolet radiation is spun on top of the fist layer and processed.  This thin top layer allows the resolution of the pattern without the adverse effects of thick resist layers or reflections from steps in the surface.  The top layer of resist, which conforms to the shape of the bottom layer and is referred to as a conformal layer, acts as a radiation block, leaving the bottom layer unpatterned.  The wafer is then given a blanket of ultraviolet exposure, which exposes the underlying positive resist through the holes in the top layer, thus extending the pattern down to the wafer surface.  A development step completes the hole resolution and the wafer is ready for etch.


The two photoresists are chosen based on compatibility throughout the process, reflection problems from the subsurface, standing waves, and sensitivity problems with PMMA resists.  Also, the two resists used must have compatible bake processes and independent developing chemistries.


Variations of the basic dual-level resist process include dyes in the PMMA and the addition of antireflection layers under the first resist layer.  The dual-level process can be used for various outcomes.  One use is as a lift-off technique.  An overhang can be created, that assists in the clean definition of the metal line on the surface, by adjusting the development of the bottom layer.


A trilevel resist process includes a hard layer between the two resist layers.  The hard layer can be a deposited layer of silicon dioxide or other developer-resistant material.  Similarly to the two layer process, the image is formed in the top photoresist layer.  Etching then transfers the image into the hard layer.  The final step is the formation of the pattern in the bottom layer, using the hard layer as an etch mask.  The hard intermediate layer allows for the use of a nonphotoresist bottom layer.

We hope that you found this review of multilayer photoresist processing helpful.  Please feel free to comment below and let the bloggers at Glew Engineering know if there is a specific topic you’d like us to blog about in the future.

Van Zant, P. (2000). Microchip fabrication, a practical guide to semiconductor processing. (4th ed.). New York, NY: McGraw-Hill.

By | 2016-12-15T22:25:25+00:00 April 4th, 2014|Materials Science, Mechanical Engineering, Semiconductor|0 Comments

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