Thermal Interface Materials use in Printed Circuit Boards
Previously, we touched upon the importance of thermal interface materials for the proper temperature regime of the CPU in your favorite PC. If it is a server or a high-performance consumer desktop CPU, then it is likely to have a large, built-in piece of metal which helps with mating the CPU to the surface of the heat sink. This also protects the silicon chip from direct mechanical interaction with the system-level components. In this case, the thermal interface material that a system manufacturer applies during the product assembly is referred to within the industry as Thermal Interface Material level Two, or TIM2. This nomenclature mirrors electronic assembly hierarchy, where connections between the component and the board levels are referred to as second level. The built-in heat spreader is analogous to the organic, or ceramic, substrate to which the silicon chip is flip-chip mounted, and whose function is, to spread out dense, first-level electrical pathways coming off silicon. A situation that occurs is the metal lid spreads out a much more disorganized form of energy flux, a heat dissipated by CPU.
First level connections
Continuing the analogy, there is an equivalent of first level connections between the CPU and the substrate. The thermal interface material, internal to the CPU package, is referred to as Thermal Interface Material level One, or TIM1. As with the first level electrical connections, choice of materials and assembly methods are more involved, compared with those in the second level. These steps are either done at a CPU maker’s facility, or at specialized manufacturing service providers. The driving issue for the complexity of mechanical connection, just as with the first level electrical connections, is thermo mechanical. If first level electrical connections require extensive engineering of solder, inter-level dielectrics and under-fill systems, first-level thermal engineering of CPU packages require management of complex curvature that develops on the chip surface due to the coefficient mismatch of thermal expansion between the chip and the substrate.